1. Field of the Invention
The present invention relates to a communication device, and more particularly, to an asynchronous communication device.
2. Background of the Related Art
Asynchronous communication is a data transmission protocol. FIG. 1 is a schematic block diagram of the prior art asynchronous communications element. The prior art asynchronous communication element is described in detail in U.S. Pat. No. 4,823,312.
Referring to FIG. 1, the prior art asynchronous communications element includes a select and control logic 54 for managing a host interface, a data bus buffer for receiving data of 8 bits, and a baud generator 26 for determining a baud rate. The device further includes a divisor latch (LS) 22, a divisor latch (MS) 24, a modem control register 48 for controlling a modem interface, and a modem status register 46 for indicating the status of the modem. Also included are an interrupt identification (ID) register 44 for indicating the order of interrupt, an interrupt enable register 32 for enabling interrupt, a line status register 34 for indicating the status of a receiver line, and a line control register 20 for determining transmitting and receiving frames.
Next, the prior art device includes a first-in-first out (FIFO) receiver 36 for receiving serial data, a receiver buffer register 28 for storing the serial data, a receiver shift register 38 for converting the received serial data into parallel data, and a receiver timing and controller for generating a clock signal to detect the received serial data. Additionally, the device has a transmitter shift register 40 for converting parallel data into serial data, a transmitter holding register 30 and a FIFO transmitter 42 for storing data to be converted into serial data, and a FIFO control register 52 for setting the environment of FIFO. Finally, a modem control logic 50 controls the modem, and a transmitter timing and controller controls the timing of the transmitter.
The operation of the aforementioned related art asynchronous communications element will now be described. For serial communications, the baud rate is determined in the host, and data are written in the divisor latches (LS, MS) 22 and 24. The baud generator 26 generates a baudout clock using the data written in the divisor latches.
To determine the data format, data are written in the line control register 20 and then a serial frame format is determined. The determined data format is communicated with a remote system through pins xe2x80x9cSINxe2x80x9d and xe2x80x9cSOUTxe2x80x9d of a serial port in response to the baud rate. For communications between the remote system and the data format, the serial port requires eight pins, such as xe2x80x9cSIN,xe2x80x9d xe2x80x9cSOUT,xe2x80x9d xe2x80x9c/RTS,xe2x80x9d xe2x80x9c/CTS,xe2x80x9d xe2x80x9c/DTR,xe2x80x9d xe2x80x9cDSR,xe2x80x9d xe2x80x9c/DCD,xe2x80x9d and xe2x80x9cRI.xe2x80x9d
The prior art asynchronous communications element has various disadvantages. For example, if two UART blocks are separately use the serial port, sixteen pins are required for the two separate serial ports. This increases the cost and occupied area, and makes the circuit unnecessarily complicated.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
The present invention substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to allow a plurality of receivers/transmitters to commonly use a serial port.
To achieve at least these advantages in a whole or in parts, there is provided an asynchronous communications element having two universal asynchronous receiver/transmitter (UART) blocks whose serial port has eight pins, includes a select control and core interface control block for generating a receiver clock (RCLK) for interface between a first UART block and a second UART block, and a common port control block for controlling the first and second UART blocks to allow the first and second UART blocks to commonly use the serial port.
In order to achieve at least the above-described objects of the present invention in a whole or in parts, there is provided a communications device including an interface circuit responsive to a clock signal and at least one feed-back control signal, a first receiver/transmitter and a second receiver/transmitter coupled to the interface circuit, the first receiver/transmitter receiving a first clock signal and data from the interface circuit to generate a first baud out signal and the second receiver/transmitter receiving a second clock signal and data from the interface circuit to generate a second baud out signal, a control circuit coupled to the first receiver/transmitter and the second receiver/transmitter and selecting one of the first and second baud out signals as an output clock signal and generating the at least one feed-back control signal for the interface circuit based on data from the first receiver/transmitter and the second receiver/transmitter, wherein the interface circuit generates the first and second clock signals based on the clock signal and the at least one feed-back signal.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided an asynchronous communications element having two Universal Asynchronous Receiver/Transmitter (UART) circuits including a control circuit, and a select control and core interface control circuit, wherein the control circuit generates a first control signal by comparing data stored in two latches, selects one of the first and second UART circuits in response to the first control signal, generates an output clock signal to control the output of the first and second UART circuits to the serial port, links signals output from the first and second UART circuits respectively with each other in response to the output clock signal, transfers the linked signals to corresponding pins of the serial port, and divides signals input through the serial port to be output to the first and second UART circuits respectively, and wherein the interface circuit generates a first clock signal and a second clock signal required for the first and second UART circuits, respectively, in response to the first control signal and a second control signal of the control circuit, and controls the first and second UART circuits to allow data input through a data bus to be input to the first and second UART circuits in response to the first and second clock signals.
To further achieve the above-described objects of the present invention in a whole or in parts, there is provided a communications device including a plurality of data receiver/transmitter circuits, and a control circuit coupled to the plurality of data receiver/transmitter circuits, wherein the control circuit controls said plurality of data receiver/transmitter circuits and allows the plurality of data receiver/transmitter circuits to send and receive data through a single serial port.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.